The above-mentioned patents, to Robert E. Swenson Ser. Nos. 207,097 and 207,152 disclose a data processing system for decreasing the average time required to access data where that data is stored on disks. A cache memory is provided and data in this memory may be accessed in a much shorter time than if the data were accessed directly from the disks. The cache memory stores segments of data, these segments containing the most recently accessed words or the words most likely to be accessed with a short interval. When a host processor wishes to access a location or locations, it sends a command to a storage control unit which first checks to see if the data from the desired locations is resident in the cache memory. If it is, the data is returned to the host if the command is a read command, and if the command is a write command then data from the host processor is written into the cache memory. If the data is not resident in the cache memory then it is staged by segments from a disk and placed in the cache memory before the host command is executed. However, before this may be accomplished, it may be necessary to delete or remove some of the segments resident in the cache memory. This is done by writing the new segments of data from the disks over selected segments in the cache memory. As taught by the aforementioned applications of Robert E. Swenson, this is accomplished by providing a segment descriptor table having an entry associated with each segment resident in the cache memory. In addition to other information relating to its associated segment, each entry in the segment descriptor table includes a forward age link address and a backward age link address whereby the segments are linked from the least recently used to the most recently used. When a segment must be replaced to make room for another segment, it is the least recently used segment which has not been written to since being staged from a disk to the cache memory that is replaced.
In the system described above, a segment is relinked at the most recently used position each time it is referenced. During what would otherwise be idle time for the storage control unit, it trickles back to the disks segments in the cache memory which have been written to by a host since they were first loaded in the cache. Segments are trickled back to the disks only if they have been written to and are then trickled back in order from the least recently used to the most recently used. As used hereinafter the term trickle defines the activity of transferring a written-to segment of data from a cache memory to a bulk memory without replacement of the segment in the cache memory.
In the foregoing system a write operation is acknowledged to the host when data from the host is written into the cache memory. Between the time a write is acknowledged to the host and the time the data is actually written to the disk (by replacement or trickling) there is a window of vulnerability to any cache memory failure such as power loss which destroys the data. To shorten this window of vulnerability it is desirable to write all modified data to the disks as soon as possible. Unfortunately, this tends to significantly increase traffic within the subsystem to the extent that a considerable part of the advantages of a cache memory may be lost. The cache aging technique of least recently used, as employed in the aforementioned Swenson patents, minimizes the number of writebacks but still produces an arbitrarily long window of vulnerability for cache segments which are frequently referenced. The present invention solves this problem by separating the replacement age of a segment (i.e. its relative eligibility for replacement with a new segment) from its writeback age (i.e. its relative eligibility for being written back or trickled to disk).